TECHNOLOGIES FOR AIR GAPS IN SEMICONDUCTOR DIES WITH ALUMINUM OXIDE LINERS
Dossier Overview
Applicant
Intel Corporation
Inventor
Akshit Peer; Ananya Dutta; Supanee Sukrittanon; Sudipto Naskar; Mauro J. Kobrinsky
IPC Classification
CPC Classification
Technologies for air gaps in semiconductor dies with aluminum oxide liners are disclosed. In an illustrative embodiment, high-aspect-ratio traces on an interconnect layer of a semiconductor die have a relatively narrow pitch. In order to reduce the capacitance between neighboring traces, an air gap is present. A liner above the air gap prevents the air gap from being filled during the semiconductor processing. In an illustrative embodiment, the liner is aluminum oxide, which may prevent stress induced leakage current (SILC) that may result when using silicon oxide or other materials.
Original (Chinese)
Technologies for air gaps in semiconductor dies with aluminum oxide liners are disclosed. In an illustrative embodiment, high-aspect-ratio traces on an interconnect layer of a semiconductor die have a relatively narrow pitch. In order to reduce the capacitance between neighboring traces, an air gap is present. A liner above the air gap prevents the air gap from being filled during the semiconductor processing. In an illustrative embodiment, the liner is aluminum oxide, which may prevent stress induced leakage current (SILC) that may result when using silicon oxide or other materials.
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