DEVICE, METHOD AND SYSTEM TO PROVIDE HETEROGENEOUS MEMORY CIRCUIT STACKING
Dossier Overview
Applicant
Intel Corporation
Inventor
Abhishek Anil Sharma; Sagar Suthram; Wilfred Gomes; Tahir Ghani; Anand Murthy; Pushkar Ranade
IPC Classification
CPC Classification
Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are variously stacked in respective face-to-back arrangements. In an embodiment, three active layers each correspond to a different respective transistor type, wherein two active layers comprise transistors of respective memory arrays, and a third active layer comprises transistors of circuitry which is coupled to access the memory arrays. In another embodiment, hybrid bond structures are disposed between two of the active layers.
Original (Chinese)
Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are variously stacked in respective face-to-back arrangements. In an embodiment, three active layers each correspond to a different respective transistor type, wherein two active layers comprise transistors of respective memory arrays, and a third active layer comprises transistors of circuitry which is coupled to access the memory arrays. In another embodiment, hybrid bond structures are disposed between two of the active layers.
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