FABRICATION OF RIBBON CFETS WITH OPTIMIZED NMOS AND PMOS CHANNEL MATERIALS
Dossier Overview
Applicant
Intel Corporation
Inventor
Guowei Xu; Robin Chao; Chia-Ching Lin; Tao Chu; Kan Zhang; Yang Zhang; Lin Hu; Ting-Hsiang Hung; Chun Wing Yeung; Feng Zhang; Chung-Hsun Lin; Oleg Golonzka; Marko Radosavljevic; Anand Murthy
IPC Classification
CPC Classification
Integrated circuit (IC) devices having stacked, complementary transistors with channels of different compositions. A device includes transistors with first and second groups of nanoribbons vertically aligned in a stack of nanoribbon channels coupling first and second sources and drains, and one of the first and second nanoribbons has a semiconductor element absent from the other. The first and second groups of nanoribbons extend between first and second spacers, which may have different compositions. First and second hardmasks with different compositions may be used process the first and second groups of nanoribbons separately. A masking layer having the composition of one of the first and second nanoribbons may mask the other of the first and second nanoribbons.
Original (Chinese)
Integrated circuit (IC) devices having stacked, complementary transistors with channels of different compositions. A device includes transistors with first and second groups of nanoribbons vertically aligned in a stack of nanoribbon channels coupling first and second sources and drains, and one of the first and second nanoribbons has a semiconductor element absent from the other. The first and second groups of nanoribbons extend between first and second spacers, which may have different compositions. First and second hardmasks with different compositions may be used process the first and second groups of nanoribbons separately. A masking layer having the composition of one of the first and second nanoribbons may mask the other of the first and second nanoribbons.
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