원래 이름 기록: SAMSUNG ELECTRONICS CO., LTD.

According to an embodiment of present disclosure, a storage controller configured to communicate with a host device may be provided. The storage controller may include a completion buffer that is configured to store one or more completions, and transmit the one or more completions to the host device; a first core that is configured to generate a first completion and a first trim load value both corresponding to a first trim command received from the host device; and a trim performance control circuit that is configured to delay transmission of the first completion to the completion buffer based on the first trim load value, with the trim performance control circuit being connected to both the completion buffer and the first core.

An electronic device includes: a display; a memory including one or more storage media storing instructions; and at least one processor including a processing circuit, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to: obtain a user query; access at least one application associated with the user query to obtain personal use data; obtain at least one search word associated with the user query from the obtained personal use data; generate at least one command by tuning the user query based on the obtained at least one search word; and display, via the display, a user interface screen in which the user query, the generated at least one command, and the obtained at least one search word are arranged according a first layout.

An electronic device may create a maximum number of frames in a frame buffer queue for a foreground application based on a plurality of frame metrics, detect a scroll operation performed on the foreground application, determine a frame rendering duration of at least one frame based on an idle time on a main thread of the foreground application after detecting the scroll operation, generate an artificial synchronization pulse for creation of additional frames for the foreground application based on the frame rendering duration of the at least one frame, adjust a timeline of a scroll animation created independently of a display synchronization pulse, and display the additional frames by filling the additional frames into the frame buffer queue until the frame buffer queue reaches a maximum capacity.

An electronic device includes: a communication circuit; a display; at least one processor; and memory storing instructions, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to: based on editing of a face included in a first image being identified, transfer, to an AI model, editing information including first information associated with the face included in the first image, the first information obtained by training a characteristic of the face selected for editing, based on receiving from the AI model a second image in which the face included in the first image is edited using the editing information, obtain a score related to a similarity between an edited face included in the second image and the face included in the first image, and based on the obtained score being greater than or equal to a threshold value, store the second image.

A wearable device may comprise: a camera; a display; at least one processor comprising processing circuitry; and a memory storing instructions, wherein at least one processor, individually and/or collectively, is configured to execute the instructions and to cause the wearable device to: receive, while a virtual space is displayed on the display, an input requesting display, on the display, of an external object within an external space around the wearable device; identify metadata corresponding to the external object designated by the input; identify a first area regarding movement of the external object, from the metadata based on the identification of the metadata; identify a first image portion of a first image, corresponding to the first area within the first image obtained by the camera; and change a first virtual space, corresponding to the first area within the virtual space and displayed on the display, to the first image portion of the first image.

A display driving unit includes a first gate driving buffer configured to supply a first gate signal to a gate line of a display panel, a second gate driving buffer configured to supply a second gate signal to the gate line, a first comparison circuit configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the second gate driving buffer, and a second comparison circuit configured to generate a signal for controlling at least one of the first gate driving buffer and the second gate driving buffer based on an output signal of the first gate driving buffer.

A display apparatus may include a frame buffer configured to sequentially receive a plurality of image frames, and a processor configured to receive the plurality of image frames from the frame buffer and identify whether a skipped frame has been generated based on the plurality of image frames, based on generation of the skipped frame, generate a predicted frame based on a preceding frame of the skipped frame among the plurality of image frames and motion information of the preceding frame, and control a display to output the predicted frame replacing the skipped frame.

A memory device is disclosed which includes a first bit line connected to a first cell string; a second bit line connected to a second cell string and adjacent to the first bit line; and a bit line precharge controller configured to control voltage levels of the first and second bit lines during an information data read operation to read data stored in the first cell string. The bit line precharge controller precharges the first bit line, provides a boost voltage to the second bit line, and then senses the data stored in the first cell string. The precharge voltage level of the first bit line is increased by the boost voltage provided to the second bit line.

In a method of reading data from a nonvolatile memory device, a first sensing operation is performed based on a first read command. While pending reception of a second read command after the first read command, voltages of a plurality of wordlines are controlled such that a voltage of a selected wordline and voltages of unselected wordlines among the plurality of wordlines have a same voltage level. A recovery operation is omitted when the second read command is received within a reference time interval. A second sensing operation is performed based on the reception of the second read command.

A semiconductor memory device includes a physical region, a direct access region and a power manager. The direct access region interfaces with an external test device directly. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage and a power supply voltage, and provides the internal power supply voltage to the direct access region. The power manager provides the second power supply voltage to the physical region. The direct access region includes a test interface circuit and the test interface circuit, in a direct access mode, generates an internal clock signal based on an external clock signal, generates an internal test clock signal by latching a test control signal received from the external test device based on the internal clock signal and provides the internal test control signal to the physical region.

A wafer chucking system includes a membrane structure including a first layer having a first coefficient of thermal expansion (CTE) on which a wafer is mountable, and a second layer having a second CTE different from the first CTE, a temperature controller configured to thermally deform the membrane structure by heating or cooling the membrane structure, and an adsorber configured to adsorb the wafer on the membrane structure.

Provided are substrate processing systems and substrate processing methods. A substrate processing method includes grinding a back side of a substrate, attaching a die attach film to the substrate that is ground, and inspecting the substrate. Inspecting the substrate includes using a vision camera to inspect a surface of the substrate, and using an infrared laser device to inspect an interior of the substrate.

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

A semiconductor device includes a lower substrate. A first pad is disposed on the lower substrate. An upper substrate is disposed on the lower substrate. A second pad is disposed in a lower portion of the upper substrate. A solder structure is disposed between the first pad and the second pad. A coating layer covers at least a portion of an external surface of the solder structure. The solder structure includes a first portion disposed on a first surface that is in contact with the first pad. The first portion has a first solder pattern and a second solder pattern. The second solder pattern surrounds the first solder pattern.

Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

Provided is a 5th-generation (5G) or 6th-generation (6G) communication system for supporting higher data rates after the 4th-generation (4G) communication system such as long term evolution (LTE). According to an embodiment of the disclosure, a user equipment (UE) may compress channel state information (CSI) data estimated between a base station (BS) and the UE through an artificial intelligence (AI) model for encoding trained in association with an AI model for decoding in the BS, transmit the compressed CSI data to the BS, transmit, to the BS, the CSI data on which the compression is not performed, based on a preset condition, and receive information for updating the AI model for encoding when the BS determines to update the AI model for encoding based on the CSI data.

An electronic device includes: a hinge structure; a foldable housing including a first housing structure and a second housing structure that are configured to be foldable relative to each other around the hinge structure; a first antenna provided in the first housing structure; a second antenna provided in the second housing structure; a communication circuit electrically connected to the first antenna and the second antenna, and configured to transmit and receive data through a first link and a second link established between an external electronic device and the electronic device; and a processor operatively connected to the communication circuit, wherein the processor is configured to: identify whether an angle between the first housing structure and the second housing structure satisfies a specified condition; and control the communication circuit to transmit, through at least one of the first link and the second link, a signal related to a change in an operation of short-range wireless communication, based on whether the angle satisfies the specified condition.

A method performed by a display apparatus, includes: outputting, by a video processor, a video frame comprising a first area corresponding to area information for the video frame; outputting a graphic frame; generating transparency information corresponding to the area information of the video frame; providing the area information of the video frame and the generated transparency information; adjusting a transparency of a second area of the graphic frame based on the area information and the transparency information; and outputting an image overlapping the video frame and the graphic frame comprising the second area having the adjusted transparency.

An electronic device includes: an image projection device; a camera; a memory storing instructions; and at least one processor including a processing circuitry. The at least one processor is configured to control the image projection device to output an image including a predetermined pattern onto a projection surface, acquire a captured image of the projection surface by using the camera, identify feature information including continuity information of a line included in the predetermined pattern in the captured image, identify at least a partial region of the projection surface as an output region based on the feature information, and control the image projection device to project an input image onto the identified output region.

An image decoding method may include: obtaining, from a sequence parameter set of a bitstream, information indicating a plurality of first reference image lists for an image sequence including a current image; obtaining, from a group header of the bitstream, an indicator for a current block group including a current block in the current image; obtaining a second reference image list by modifying a first reference image list indicated by the indicator, from among the plurality of first reference image lists, into the second reference image list; and prediction-decoding a lower block of the current block based on a second reference image included in the second reference image list.